The invention relates generally to clock pulse generation circuits and deals more particularly with a clock pulse generation circuit with a controlled output to reduce pulse width yet satisfy a wide range of loads.
Master/slave flip-flops are well known in the industry. Typically, the master latch is set with one clock pulse and the input data is transferred to the slave latch using a subsequent independent clock pulse. One shortcoming of this arrangement is the need for two separate clock signals. This may require two separate clocks and will require two circuit lines to deliver the two, nonoverlapping clock signals to the flip-flop. In very fast circuits, care must be taken to ensure that the two circuit lines have similar length so that the two clock signals arrive at the flip-flop in proper timed relation. Alternately, delay circuits can be added to compensate for differences in the length of the circuit lines for the two clock signals. Nevertheless, even if the clock signals arrive at the pre-determined time, this arrangement does not take into account differences in load. With a large load, i.e. substantial current drain and capacitance, the voltage of the pulse will rise gradually, and a longer pulse width will be required to allow the pulse to rise to an effective voltage level to drive the load. Conversely, with a small load, a shorter pulse width will be adequate.
It was also known in master/slave flip-flops to maintain the clock input to the slave latch active and pulse the clock line of the master. This eliminates the balancing of the master and slave latch clock distribution networks and reduces power consumption. However, care must be taken to control the shape of input clock pulse to the master latch. In the prior art, the clock pulse output from the master/slave flip-flop was generated without regard to the electrical characteristics of the network that it feeds.
A simplified version of a single clock, pulse generation circuit generally designated 6 is shown in FIG. 1 (labelled as xe2x80x9cPrior Artxe2x80x9d). Initially, a clock signal 8 is in the steady-state low condition, the output of inverter 14 is high and the output of delay circuit 16 is high. Because of the clock signal being low, the output of nand gate 10 is high and the output of inverter/driver 12 is low. Then, to initiate a pulse output from inverter/driver 12, the clock signal 8 goes high. At this instant the output of delay circuit 16 is still high, so the output of nand gate 10 momentarily goes low and the output of inverter/driver 12 momentarily goes high to initiate the desired output pulse. A short time later, the high level of the clock signal 8 passes through the inverter 14 and the delay circuit 16 to apply a low level to the input of nand gate 10. This causes the nand gate 10 to output a high level again and the output of inverter/driver 12 to output a low level again. Thus, the duration of the output pulse from inverter/driver 12 is determined by the propagation delay through inverter 14 and delay 16. While this arrangement operates from a single clock signal, the output pulse width is fixed and is not tailored to the load.
Accordingly, an object of the present invention is to provide a flip-flop or pulse generation circuit which is driven by a single clock signal and has a pulse width tailored to the load.
The invention resides in the following pulse generation circuit having a tailored output pulse. A drive circuit has an input coupled to receive a clock signal and an output coupled to drive a load. A comparator has an input coupled to the output of the drive circuit. Another input of the comparator is supplied by a reference voltage. A feedback circuit comprises logic gates and has an input coupled to an output of the comparator. An output of the feedback circuit is coupled to another input of the drive circuit to terminate a pulse output from the drive circuit when a voltage output from the drive circuit exceeds the reference voltage. The reference voltage is higher than a voltage required to trigger the logic gates and a voltage required to drive the load. This ensures that the load is driven adequately over a wide range of load currents and capacitances. By setting the reference voltage between the voltage required to drive the load and the supply voltage, the pulse width is not excessive.